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? semiconductor components industries, llc, 2006 february, 2006 ? rev. 8 1 publication order number: cs51021a/d cs51021a, cs51022a, cs51023a, cs51024a enhanced current mode pwm controller the cs51021a/2a/3a/4a fixed frequency pwm current mode controller family provides all necessary features required for ac?dc or dc?dc primary side control. several features are included eliminating the additional components needed to implement them externally. in addition to low startup current (75 a) and high frequency operation capability, the cs51021a/2a/3a/4a family includes overvoltage and undervoltage monitoring, externally programmable dual threshold overcurrent protection, current sense leading edge blanking, current slope compensation, accurate duty cycle control and an externally available 5.0 v reference. the cs51021a and cs51023a feature bidirectional synchronization capability , while the cs51022a and cs51024a offer a sleep mode with 100 a maximum ic current consumption. the cs51021a/2a/3a/4a family is available in a 16 lead narrow body soic package. device sleep/synch v cc start/stop cs51021a synch 8.25 v/7.7 v cs51022a sleep 8.25 v/7.7 v cs51023a synch 13 v/7.7 v cs51024a sleep 13 v/7.7 v features ? 75 a max. startup current ? fixed frequency current mode control ? 1.0 mhz switching frequency ? undervoltage protection monitor ? overvoltage protection monitor with programmable hysteresis ? programmable dual threshold overcurrent protection with delayed restart ? programmable soft start ? accurate maximum duty cycle limit ? programmable slope compensation ? leading edge current sense blanking ? 1.0 a sink/source gate drive ? bidirectional synchronization (cs51021a/3a) ? 50 ns pwm propagation delay ? 100 a max sleep current (cs51022a/4a) ? pb?free packages are available* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. x = specific device code a = assembly location wl, l = wafer lot y = year ww, w = work week g or = pb?free package soic?16 d suffix case 751b 1 16 v fb i set 1 cs5102xag awlyww 16 comp r t c t ss ov lgnd uv v ref slope v cc sleep or sync pgnd i sense v c gate pin connections and marking diagrams http://onsemi.com 1 16 tssop?16 dtb suffix case 948f cs51 022a alyw 116 see detailed ordering and shipping information in the packag e dimensions section on page 9 of this data sheet. ordering information
cs51021a, cs51022a, cs51023a, cs51024a http://onsemi.com 2 v c v ref comp v fb r t c t sync/ c ss v cc uv ov i set slope gate i sense pgnd cs51021a/2a lgnd sleep 22 k 4700 pf 51 k 10 k 0.01 f 24.3 k, 1.0% 200 k, 1.0% 2.49 k, 1.0% ba521 irf6345 6.98 k, 1.0% 6.98 k, 1.0% 470 pf 100 p 100 10 k 62 680 pf 100 f 100 f v out sgnd (5 v/5 a) 10 fzt688 sync/sleep 22 f 18 v bas21 51 k 11 v (36 v to 72 v) pgnd 0.01 f 1.0 f 100 100:1 4:1 2:5 10 v in moc81025 tl431 1000 pf 5.1 k 0.1 f 2.0 k, 1.0% 2.0 k, 1.0% 1.0 k 180 1.0 k 10 k 330 pf figure 1. typical application diagram, 36?72 v to 5.0 v, 5.0 a dc?dc converter maximum ratings* rating value unit power supply voltage, v cc ?0.3, 20 v driver supply voltage, v c ?0.3, 20 v sync, sleep, r t c t , soft?start, v fb , slope, i sense , uv, ov, i set (logic pins) 0.25 to v ref v peak gate output current 1.0 a steady state output current 0.2 a operating junction temperature, t j 150 c storage temperature range, t s ?65 to +150 c esd (human body model) 2.0 kv lead temperature soldering: reflow: (smd styles only) (note 1) 230 peak c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. *the maximum package power dissipation must be observed. 1. 60 second maximum above 183 c.
cs51021a, cs51022a, cs51023a, cs51024a http://onsemi.com 3 electrical characteristics (unless otherwise stated, specifications apply for ?40 c < t a < 85 c, ?40 c < t j < 150 c, 3.0 v < v c < 20 v, 8.2 v < v cc < 20 v, r t = 12 k , c t = 390 pf) characteristic test conditions min typ max unit under voltage lockout start threshold (cs51021a/2a) ? 7.95 8.25 8.8 v start threshold (cs51023a/4a) ? 12.4 13 13.4 v stop threshold ? 7.4 7.7 8.2 v hysteresis (cs51021a/2a) ? 0.50 0.75 1.00 v hysteresis (cs51023a/4a) ? 4.0 5.0 6.0 v i cc @ startup (cs51021a/2a) v cc < uv start threshold ? 40 75 a i cc @ startup (cs51023a/4a) v cc < uv start threshold ? 45 75 a i cc operating (cs51021a/3a) ? ? 7.0 9.0 ma i cc operating (cs51022a/4a) ? ? 6.0 8.0 ma i cc operating includes 1.0 nf load ? 7.0 12 ma voltage reference initial accuracy t a = 25 c, i ref = 2.0 ma, v cc = 14 v, (note 2) 4.95 5.0 5.05 v total accuracy 1.0 ma < i ref < 10 ma 4.9 5.0 5.15 v line regulation 8.2 v < v cc < 18 v, i ref = 2.0 ma ? 6.0 20 mv load regulation 1.0 ma < i ref < 10 ma ? 6.0 15 mv noise voltage (note 2) ? 50 ? v op life shift t = 1000 hours, (note 2) ? 4.0 20 mv fault voltage force v ref 0.90 v ref 0.93 v ref 0.95 v ref v ok voltage force v ref 0.94 v ref 0.96 v ref 0.985 v ref v ok hysteresis force v ref 75 165 250 mv current limit force v ref ?20 ? ? ma error amplifier initial accuracy t a = 25 c, i ref = 2.0 ma, v cc = 14 v, v fb = comp, (note 2) 2.465 2.515 2.565 v reference voltage v fb = comp 2.440 2.515 2.590 v v fb leakage current v fb = 0 v ? ?0.2 ?2.0 a open loop gain 1.4 v < comp < 4.0 v, (note 2) 60 90 ? db unity gain bandwidth (note 2) 1.5 2.5 ? mhz comp sink current comp = 1.5 v, v fb = 2.7 v 2.0 6.0 ? ma comp source current comp = 1.5 v, v fb = 2.3 v ?0.2 ?0.5 ? ma comp high voltage v fb = 2.3 v 4.35 4.8 5.0 v comp low voltage v fb = 2.7 v 0.4 0.8 1.2 v ps ripple rejection freq = 120 hz, (note 2) 60 85 ? db ss clamp, v comp v ss = 2.5 v, v fb = 0 v, i set = 2.0 v 2.4 2.5 2.6 v i lim(set) clamp (note 2) 0.95 1.0 1.15 v 2. guaranteed by design, not 100% tested in production.
cs51021a, cs51022a, cs51023a, cs51024a http://onsemi.com 4 electrical characteristics (unless otherwise stated, specifications apply for ?40 c < t a < 85 c, ?40 c < t j < 150 c, 3.0 v < v c < 20 v, 8.2 v < v cc < 20 v, r t = 12 k , c t = 390 pf) characteristic unit max typ min test conditions oscillator accuracy r t = 12 k, c t = 390 pf 230 255 280 khz voltage stability delta frequency 8.2 v < v cc < 20 v ? 2.0 3.0 % temperature stability t min < t a < t max, (note 3) ? 8.0 ? % min charge & discharge time (note 3) 0.333 ? ? s duty cycle accuracy r t = 12 k, c t = 390 pf 70 77 83 % peak voltage (note 3) ? 3.0 ? v valley voltage (note 3) ? 1.5 ? v valley clamp voltage 10 k resistor to ground on r t c t 1.2 1.4 1.6 v discharge current ? 0.8 1.0 1.2 ma discharge current ta = 25 c, note 3 0.925 1.0 1.075 ma synchronization (cs51021a/3a) input threshold ? 1.0 1.5 2.7 v output pulsewidth ? 160 260 400 ns output high voltage i sync = 100 a 3.5 4.3 4.8 v input resistance (note 3) 35 70 140 k drive delay sync to gate reset 80 120 150 ns output drive current 1.0 k load 1.25 2.0 3.5 ma sleep (cs51022a/4a) sleep input threshold active high 1.0 1.5 2.7 v sleep input current v sleep = 4.0 v 11 25 46 a i cc @ sleep v cc 15 v ? 50 100 a gate driver high voltage measure v c ? gate, v c = 10 v, 150 ma load ? 1.5 2.2 v low voltage measure gate ? pgnd, 150 ma sink ? 1.2 1.5 v high voltage clamp v c = 20 v, 1.0 nf 11 13.5 16 v low voltage clamp measured at 10 ma output current ? 0.6 0.8 v peak current v c = 20 v, 1.0 nf, (note 3) ? 1.0 ? a uvl leakage v c = 20 v measured at 0 v ? ?1.0 ?50 a rise time load = 1.0 nf, 1.0 v < gate < 9.0 v, v c = 20 v, t a = 25 c ? 60 100 ns fall time load = 1.0 nf, 9.0 v > gate > 1 .0 v, v c = 20 v ? 15 40 ns slope compensation charge current slope = 2.0 v ?63 ?53 ?43 a comp gain fraction of slope voltage added to i sense , (note 3) 0.095 0.100 0.105 v/v discharge voltage sync = 0 v ? 0.1 0.2 v 3. guaranteed by design, not 100% tested in production.
cs51021a, cs51022a, cs51023a, cs51024a http://onsemi.com 5 electrical characteristics (unless otherwise stated, specifications apply for ?40 c < t a < 85 c, ?40 c < t j < 150 c, 3.0 v < v c < 20 v, 8.2 v < v cc < 20 v, r t = 12 k , c t = 390 pf) characteristic unit max typ min test conditions current sense offset voltage (note 4) 0.09 0.10 0.11 v blanking time ? ? 55 160 ns blanking disable voltage adjust v fb 1.8 2.0 2.2 v second current threshold gain ? 1.21 1.33 1.45 v/v i sense input resistance ? ? 5.0 ? k minimum on time gate high to low 30 70 110 ns gain (note 4) 0.78 0.80 0.82 v/v ov & uv voltage monitors ov monitor threshold ? 2.4 2.5 2.6 v ov hysteresis current ? ?10 ?12.5 ?15 a uv monitor threshold ? 1.38 1.45 1.52 v uv monitor hysteresis ? 25 75 100 mv soft start (ss) charge current ss = 2.0 v ?70 ?55 ?40 a discharge current ss = 2.0 v 250 1000 ? a charge voltage, v ss ? 4.4 4.7 5.0 v discharge voltage, v ss ? 0.25 0.27 0.30 v 4. guaranteed by design, not 100% tested in production. package pin description pin # pin symbol function 16 lead so narrow 1 gate external power switch driver with 1.0 a peak capability. 2 i sense current sense amplifier input. 3 sync (cs51021a/3a) bi?directional synchronization. locks to the highest frequency. 3 sleep (cs51022a/4a) active high chip disable. in sleep mode, v ref and gate are turned off. 4 slope additional slope to the current sense signal. internal current source charges the external capacitor. 5 uv undervoltage protection monitor. 6 ov overvoltage protection monitor. 7 r t c t timing resistor r t and capacitor c t determine oscillator frequency and maximum duty cycle, d max. 8 i set voltage at this pin sets pulse?by?pulse overcurr ent threshold, and second threshold (1.33 times higher) with soft start retrigger (hiccup mode). 9 v fb feedback voltage input. connected to the error amplifier inverting input. 10 comp error amplifier output. frequency compensation network is usually connected between comp and v fb pins. 11 ss charging external capacitor restricts error amplifier output voltage during the start or fault conditions (hiccup). 12 lgnd logic ground. 13 v ref 5.0 v reference voltage output. 14 v cc logic supply voltage. 15 pgnd output power stage ground connection. 16 v c output power stage supply voltage.
cs51021a, cs51022a, cs51023a, cs51024a http://onsemi.com 6 d 2 start + ? stop ss + ? clamp e/a + ? i set ? + clamp d 3 d 1 20 k 10 k v fb ? + monitor g 4 pwm ? + comp 55 ns blank i sense s lope v fb c omp r t c t 2nd + ? threshold ov + ? monitor disable 0.1 0.8 q 2 1.33 53 a i set ov 12.5 a v ref 2.5 v + ? + ? 2.0 v + ? 2.5 v v ref v isense ss ? + monitor discharge latch uv ? + monitor 1.45 v + ? 4.7 v + ? s r q f 1 g 1 g 2 d 4 zd 1 13.5 v v c gate pgnd ss uv g 3 fault 55 a v ref osc sync 4.3 v 200 ns ? + v ref _ok + ? 4.75 v v ref = 5.0 v + ? + ? 0.1 v v cc _ok v ref s leep lgnd v cc figure 2. block diagram
cs51021a, cs51022a, cs51023a, cs51024a http://onsemi.com 7 circuit description sync r t c t slop e is v ds 0 v 0 v 0 v 0 v 0 v v in 0 v v comp pwm comp gate 4.3 v 200 ns t ch t dis v slope 55 ns blanking is + 0.1 slope is figure 3. typical waveforms theory of operation powering the ic the ic has two supply and two ground pins. v c and pgnd pins provide high speed power drive for the external power switch. v cc and lgnd pins power the control portion of the ic. the internal logic monitors the supply voltage, v cc . during abnormal operating conditions, the output is held low. the cs51021a/2a/3a/4a requires only 75 a of startup current. voltage feedback the output voltage is monitored via the v fb pin and is compared with the internal 2.5 v reference. the error amplifier output minus one diode drop is divided by 3 and connected to the negative input of the pwm comparator. the positive input of the pwm comparator is connected to the modified current sense signal. the oscillator turns the external power switch on at the beginning of each cycle. when current sense ramp voltage exceeds the reference side of pwm comparator, the output stage latches off. it is turned on again at the beginning of the next oscillator cycle. current sense and protection the current is monitored at the i sense pin. the cs51021a/2a/3a/4a has leading edge blanking circuitry that ignores the first 55 ns of each switching period. blanking is disabled when v fb is less than 2.0 v so that the minimum on?time of the controller does not have an additional 55 ns of delay time during fault conditions. for the remaining portion of the switching period, the current sense signal, combined with a fraction of the slope compensation voltage, is applied to the positive input of the pwm comparator where it is compared with the divided by three error amplifier output voltage. the pulse?by?pulse overcurrent protection threshold is set by the voltage at the i set pin. this voltage is passed through the i set clamp and appears at the non?inverting input of the pwm comparator, limiting its dynamic range according to the following formula: overcurrent threshold 0.8 v i(sense) 0.1 v 0.1 v slope where v i(sense) is voltage at the i sense pin. and v slope is voltage at the slope pin. during extreme overcurrent or short circuit conditions, the slope of the current sense signal will become much steeper than during normal operation. due to loop propagation delay, the sensed signal will overshoot the pulse?by?pulse threshold eventually reaching the second overcurrent protection threshold which is 1.33 times higher than the first threshold and is described by the following equation: 2nd threshold 1.33 v i(set) exceeding the second threshold will reset the soft start capacitor c ss and reinitiate the soft start sequence, repeating for as long as the fault condition persists. soft start during power up, when the output filter capacitor is discharged and the output voltage is low, the voltage across the soft start capacitor (v ss ) controls the duty cycle. an internal current source of 55 a charges c ss . the maximum error amplifier output voltage is clamped by the ss clamp. when the soft start capacitor voltage exceeds the error amplifier output voltage, the feedback loop takes over the duty cycle control. the soft start time can be estimated with the following formula: t ss 9 10 4 c ss the soft start voltage, v ss , charges and discharges between 0.25 v and 4.7 v.
cs51021a, cs51022a, cs51023a, cs51024a http://onsemi.com 8 slope compensation dc?dc converters with current mode control require a current sense signal with slope compensation to avoid instability at duty cycles greater than 50%. slope capacitor c s is charged by an internal 53 a current source and is discharged during the oscillator discharge time. the slope compensation voltage is divided by 10 and is added to the current sense voltage, v i(sense) . the signal applied to the input of the pwm comparator is a combination of these two voltages. the slope compensation, dv slope /dt , is calculated using the following formula: dv slope dt 0.1 53 a c s it should be noted that internal capacitance of the ic will cause an error when determining slope compensation capacitance c s . this error is typically small for large values of c s , but increases as c s becomes small and comparable to the internal capacitance. the effect is apparent as a reduction in charging current due to the need to charge the internal capacitance in parallel with c s .figure 4 shows a typical curve indicating this decrease in available char ging current. figure 4. the slope compensation pin charge current reduces when a small capacitor is used. 10 100 1000 60 55 50 45 40 35 30 25 20 charging current ( a) compensation cap (pf) undervoltage (uv) and overvoltage (ov) monitor two independent comparators monitor ov and uv conditions. a string of three resistors is connected in series between the monitored voltage (usually the input voltage) and ground (see figure 5). when voltage at the ov pin exceeds 2.5 v, an overvoltage condition is detected and gate shuts down. an internal 12.5 a current source turns on and feeds current into the external resistor, r 3 , creating a hysteresis determined by the value of this resistor (the higher the value, the greater the hysteresis). the hysteresis voltage of the ov monitor is determined by the following formula: v ov(hyst) 12.5 a r 3 where r 3 is a resistor connected from the ov pin to ground. when the monitored voltage is low and the uv pin is less than 1.45 v, gate shuts down. the uv pin has fixed 75 mv hysteresis. both ov and uv conditions are latched until the soft start capacitor is discharged. this way, every time a fault condition is detected the controller goes through the power up sequence. figure 5. uv/ov monitor divider v in v uv v ov r 1 r 2 r 3 to calculate the ov?uv resistor divider : 1. solve for r 3 , based on ov hysteresis requirements. r 3 v ov(hyst) 2.5 v v max 12.5 a where v ov(hyst) is the desired amount of overvoltage hysteresis, and v max is the input voltage at which the supply will shut down. 2. find the total impedance of the divider. r tot r 1 r 2 r 3 v max r 3 2.5 3. determine the value of r 2 from the uv threshold conditions. r 2 1.45 r tot v min r 3 where v min is the uv voltage at which the supply will shut down. 4. calculate r 1 . r 1 r tot r 2 r 3 5. the undervoltage hysteresis is given by : v uv(hyst) v min 0.075 1.45 v ref monitor the 5.0 v reference voltage is internally monitored to ensure that it remains within specifications. the monitor, which outputs a fault, can be tripped by two methods: ? if the reference voltage drops below 4.75 v ? if v cc falls below the stop threshold as indicated in the block diagram, any fault causes the output to stop switching and begins the discharge of the soft start capacitor c ss .
cs51021a, cs51022a, cs51023a, cs51024a http://onsemi.com 9 synchronization a bi?directional synchronization is provided to synchronize several controllers. when sync pins are connected together, the converters will lock to the highest switching frequency. the fastest controller becomes the mas ter, producing a 4.3 v, 200 ns pulse train. only one, the highest frequency sync signal, will appear on the sync line. sleep the sleep input is an active high input. the cs51022a/4a is placed in sleep mode when sleep is driven high. in sleep mode, the controller and mosfe t are turned off. connect to gnd for normal operation. the sleep mode operates at vcc 15 v. oscillator and duty cycle limit the switching frequency is set by r t and c t connected to the r t c t pin. c t charges and discharges between 3.0 v and 1.5 v. the maximum duty cycle is set by the ratio of the on time, t on , and the whole period, t = t on + t off . because the timing capacitor?s discharge current is trimmed, the maximum duty cycle is well defined. it is determined by the ratio between the timing resistor r t and the timing capacitor c t . refer to figures 6 and 7 to select appropriate values for r t and c t . f sw 1 t sw ;t sw t ch t dis 5 2500 frequency (khz) r t (k ) 2000 1500 1000 500 0 100 90 80 70 60 50 40 10 15 20 25 30 35 40 45 50 5 10 15 20 25 30 35 40 45 50 5 5 r t (k ) duty cycle (%) 1 2 3 4 5 6 8 7 2 1 3 4 8 7 5 6 1. c t = 47 pf 2. c t = 100 pf 3. c t = 150 pf 4. c t = 220 pf 5. c t = 390 pf 6. c t = 470 pf 7. c t = 560 pf 8. c t = 680 pf 1. c t = 47 pf 2. c t = 100 pf 3. c t = 150 pf 4. c t = 220 pf 5. c t = 390 pf 6. c t = 470 pf 7. c t = 560 pf 8. c t = 680 pf figure 6. frequency vs. r t for discrete capacitor values figure 7. duty cycle vs. r t for discrete capacitor values ordering information device package shipping ? cs51021aed16 soic?16 48 units / rail cs51021aedr16 2500 tape & reel CS51021AEDR16G soic?16 (pb?free) cs51022adbg tssop?16* 48 units / rail cs51022adbr2g tssop?16* 2500 tape & reel cs51022aed16 soic?16 48 units / rail cs51022aedr16 2500 tape & reel cs51022aedr16g soic?16 (pb?free) cs51023aed16 soic?16 48 units / rail cs51023aedr16 2500 tape & reel cs51023aedr16g soic?16 (pb?free) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb?free.
cs51021a, cs51022a, cs51023a, cs51024a http://onsemi.com 10 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 soic?16 d suffix case 751b?05 issue j package thermal data parameter soic?16 unit r jc typical 28 c/w r ja typical 115 c/w
cs51021a, cs51022a, cs51023a, cs51024a http://onsemi.com 11 ??? ??? ??? 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. section n?n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 16x ref k n n tssop?16 case 948f?01 issue a on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 cs51021/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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